With the continue scaling of transistor feature sizes, VLSI chip density continue increases. This results in a continue increase in the complexity VLSI technology where it has reached the point where billions of transistors are integrated on a single chip (like it is the case for System on Chip). To guarantee the satisfaction of the customers, the produced VLSI chips have to be reliable and fully tested. Verification testing and production testing represents 50 t0 60% of the cost of making VLSI chips, and are now the biggest cost of the technology.
It has been known for a while that tackling the problems associated with testing VLSI chips at earlier design stage levels significantly reduces testing cost. Thus it is important for hardware designers to be exposed to concepts of VLSI testing which can help them design better product at lower cost. This course is an introduction to the field of digital systems testing, which is an integral part of IC design and manufacturing. The topics discussed are: Importance of VLSI Testing, Test process and Automatic Test Equipment, Defects versus Fault models, Fault simulation, Logic simulation, Combinational Circuit Testing, Sequential Circuit Testing, Memory Testing, Design-for-Testability, Scan Design, Boundary Scan, Built-in-Self Test, Delay Test, Current Testing, VLSI Reliability, etc.
- VLSI Test Process and Test Equipment
- Fault Modeling
- Logic and Fault Simulation
- Testability Measures
- Combinational Circuit Testing
- Sequential Circuit Testing
- Memory Testing
- Delay Testing
- Current testing
- Built-In-Self Test
- Digital DFT and Scan Design
- Boundary Scan Standard
- Semiconductor Reliability
VLSI Test Technology & Reliabillity by TU Delft OpenCourseWare is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.
Based on a work at https://ocw.tudelft.nl/courses/vlsi-test-technology-reliabillity/.