This module is about logic and fault simulations. The first half of the slides is dedicated to logic simulation and the second half to fault simulation.

The logic simulation part starts with its definition, followed by an explanation on simulation for design verification and simulation models. A distinction is made between compiled-code simulation and event-driven simulation.

Next, the topic of fault simulation is discussed. A typical fault simulation problem is given and a fault simulator for test is discussed. Thereafter, four fault simulation algorithms are discussed: serial, parallel, deductive and concurrent. Finally, alternatives to fault simulation are given.

Corresponding to material treated in this module come the following textbook chapters: Chapter 5.