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VHDL signals, delays, processes, generics en configurations

Course subject(s) 05. VHDL signals, delays, processes, generics en configurations

De volgende onderwerpen worden behandeld:

  • Discrete Event Simulator,
  • Modelleren van complex gedrag->process, Simpele “programmeer” -constructs,
  • Variabelen vs. Signalen,
  • Wait statements,
  • State machines in VHDL (een voorbeeld),
  • Hiërarchie van componenten,
  • Generics,
  • Configuraties.

Lezen: (Student’s Guide to VHDL, P.J. Ashenden, Morgan-Kaufmann).

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