The readings for this course consist, next to the lecture slides, of one book. The book is named Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits – by M.L. Bushnell and V.D. Agrawal. Published in 2000 by Springer. ISBN 0-7923-799-1-8. You can view a number of pages for free under this google books link.
Summary of the book
The textbook consists of three parts that span in total 19 chapters. Below, a short overview of the contents of each part is given below. You can use this to find out which chapters deal with which concepts, or use it as a checklist: do you know what all the definitions mean, and how to apply all the methods?
For this course, chapters 10, 11, 17, 18 and 19 are not treated and will therefore not be summarized on this page.
Part 1: Introduction to Testing
Chapter 1. Introduction
This first chapter is, as the name implies, an introduction to the topic of testing. In this chapter, testing philosophy is treated and the importance of testing is elaborated. Furthermore, digital and analog VLSI testing is treated.
Chapter 2. VLSI Testing Process and Test Equipment
This chapter discusses how to test chips. Automatic test equipment is treated, as well as electrical parametric testing.
Chapter 3. Test Economics and Product Quality
This chapter is mainly about test economics. The topic of yield is introduced and defect level as a quality measure is explained.
Chapter 4. Fault Modeling
This chapter deals with defects, errors and faults. Functional testing is compared with structural testing. Also, levels of fault models are explained and single stuck-at fault is treated.
Part 2: Test Methods
Chapter 5. Logic and Fault Simulation
This first chapter on test methods treats simulation for design verification and for test evaluation. Furthermore, modeling circuits for simulation are elaborated. Also, algorithms for true-value and fault simulations are explained. Lastly, statistical methods for fault simulation are treated.
Chapter 6. Testability Measures
This chapter is mainly about SCOAP controllability and observability, where a difference is made between combinational and sequential SCOAP measures. Furthermore, high-level testability measures are explained.
Chapter 7. Combinational Circuit Test Generation
This chapter starts with the explanation of several algorithms and representations. Next, the topic of redundancy identification (RID) is treated. Also, significant combinational ATPG algorithms are specifically treated. Furthermore, test generation systems and test compaction is elaborated.
Chapter 8. Sequential Circuit Test Generation
First, ATPG for single-clock synchronous circuits is explained and a simplified problem is worked out. The next topic in this chapter is about the time-frame expansion method and the chapter is closed with an explanation on simulation-based sequential circuit ATPG.
Chapter 9. Memory Test
The ninth chapter of the book deals with the memory test method. First, memory density and defect trends are treated and an introduction to the common notations is given. Thereafter, the memory test methods is treated thoroughly.
Chapter 12. Delay Test
This chapter is about the delay test method. First a problem is worked out and then the path-delay test is elaborated. Furthermore, transition faults and delay test methodologies are explained. Lastly, practical considerations in delay testing are treated.
Chapter 13. IDDQ Test
This chapter is about the current (IDDQ) test method. Faults detected by IDDQ tests are treated, as well as several IDDQ testing methods. Also, the effectiveness and the limitations of this method is discussed.
Part 3: Design for Testability
Chapter 14. Digital DFT and Scan Design
The first chapter in this part on DFT deals with digital DFT and with scan design. First, as-hoc DFT methods are listed and discussed. Thereafter, the topic of scan design is introduced. Also, partial-scan design is treated in this chapter.
Chapter 15. Built-in Self-test
This chapter is about BIST and it starts with the economic case for BIST. Then, the random logic BIST and its definitions are explained, as well as the memory BIST. In the last part of this chapter, the topic of delay fault BIST is treated.
Chapter 16. Boundary Scan Standard
This chapter first starts with a motivation on the purpose of this standard. Furthermore, system configurations with boundary scans are explained and with it comes the boundary scan description language.
VLSI Test Technology & Reliabillity by TU Delft OpenCourseWare is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.
Based on a work at https://ocw.tudelft.nl/courses/vlsi-test-technology-reliabillity/.